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[VHDL-FPGA-Verilog] grlib-tmtc-1.0.18.tar

Description: Zipped LEON3 processor VHDL core.
Platform: | Size: 1452032 | Author: AcousticMan | Hits:

[VHDL-FPGA-Verilog] rax2

Description: rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
Platform: | Size: 1024 | Author: LL | Hits:

[VHDL-FPGA-Verilog] pipelined_fft_64

Description: 利用IP Core编写的Verilog程序，实现FFT变换，希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
Platform: | Size: 99328 | Author: chengyungang | Hits:

[VHDL-FPGA-Verilog] 8051vlog

Description: 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
Platform: | Size: 251904 | Author: zhangq | Hits:

[VHDL-FPGA-Verilog] CoreCFI

Description: VERILOG编写的CoreCFI实验例程，包括整个工程，可以直接使用-Prepared CoreCFI VERILOG test routines, including the whole project, can be used directly
Platform: | Size: 862208 | Author: xuzunlei | Hits:

[VHDL-FPGA-Verilog] 8088verilog

Description: intel8088的verilog core ，完整的RTL-intel 8088 verilog core， all RTL
Platform: | Size: 206848 | Author: zhangq | Hits:

[VHDL-FPGA-Verilog] Q8051

Description: A 1T51 core which contain 16 verilog files. this mcu core consiste with standard 51
Platform: | Size: 34816 | Author: 艾瑞庭 | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
Platform: | Size: 1487872 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
Platform: | Size: 36864 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
Platform: | Size: 13312 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] USB2.0-IP-core

Description: 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
Platform: | Size: 200704 | Author: 柳同学 | Hits:

[VHDL-FPGA-Verilog] DW8051_core

Description: 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
Platform: | Size: 438272 | Author: gaoming | Hits:

[VHDL-FPGA-Verilog] 61EDA_C1910

Description: ARM9架构简单CORE实现，可以综合，有实现步骤和说明，Verilog代码编写-ARM9 CORE achieve simple structure, can be integrated, with implementation steps and instructions, Verilog coding
Platform: | Size: 948224 | Author: liumeng | Hits:

[VHDL-FPGA-Verilog] fft_2011_3_23(COMPLETE-FFT1024)

Description: VERILOG FFT IP核调用，以及其控制文件-VERILOG FFT IP core call, as well as its control file
Platform: | Size: 20978688 | Author: 贾斌 | Hits:

[VHDL-FPGA-Verilog] I2C-Master-_-Slave-Core

Description: 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
Platform: | Size: 2181120 | Author: 郭天然 | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] synth_fft

Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT.
Platform: | Size: 56320 | Author: zzy | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE
Platform: | Size: 67584 | Author: hebin | Hits:

[VHDL-FPGA-Verilog] UDP_Core

Description: 本人用verilog编写的UDP协议，经测试可用。-I am prepared to use verilog UDP protocol, the test is available.
Platform: | Size: 2048 | Author: yaicity | Hits:
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